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Workshop on Programming Massively Parallel Processors (PMPP) July 10, 2008 Until recently, computer performance improvements were largely driven by the ever-increasing clock speed of commodity microprocessors. As semiconductor devices shrink to enable higher clock rates, poor wire scaling becomes the performance-limiting bottleneck. In order to take advantage of the shrinking transistor size and alleviate the poor wire scaling, semiconductor manufacturers resort to placing multiple copies of the same design on a single die instead of increasing the clock speed. Multi-core chips, unheard of just a few years ago, are a standard today. While the general-purpose processors are still restricted to just a few cores per die, more specialized chips, such as stream processors used in computer graphics applications, contain hundreds of smaller well-tuned SIMD-enabled cores capable of running thousands of execution threads. With the 128-core GeForce 8800 chip from NVIDIA and the announcement of Fusion from AMD (consisting of a mix of graphics processors and scalar processing cores), the genesis of heterogeneous terascale class chip multiprocessing has begun. Co-sponsored by the National Center for Supercomputing Applications (NCSA) and the Institute for Advanced Computing Applications and Technologies (IACAT), and co-located with the 2008 Reconfigurable Systems Summer Institute (RSSI), the Workshop on Programming Massively Parallel Processors will bring together researchers, industry, and users concerned with the issue of programming multi-core and many-core architectures for productive use in applications ranging from desktop to high-performance computing systems. The workshop will include presentations from industry leaders and early technology adopters and will stimulate the dialogue among researchers about programming models, languages, and tools that the community is lacking in order to take advantage of the emerging multi-core and many-core architectures. Topics will include:
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